In current semiconductor processing for 10 nm schemes, a tonen silazene (TOSZ) is used as a gapfill material between gates and a high density plasma (HDP) oxide is used as an interlayer dielectric (ILD). After dummy gate polysilicon removal, during I/O device gate oxide etch with dilute hydrofluoric acid (dHF) and chemical oxide removal (COR), about 12 nm of the ILD is lost. Another 15 nm of ILD is lost during reactive ion etching (RIE), recessing the metal gate, due to the selectivity issue of metal to oxide. In addition, 5 nm more are lost during removal of a silicon nitride (SiN) gate cap by chemical mechanical polishing. This ILD loss is referred to as ILD dishing. As a result of ILD dishing an increased polysilicon dummy gate height budget (specifically about 32 nm) is necessary to compensate for the loss of ILD material.
A need therefore exists for improved methodology that mitigates ILD dishing and effectively reduces gate height budget requirements.